Microcom ez br2 manual

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For further information on how we protect your information, please refer to our Privacy Notice. Heavy Loads, High Speeds, Long Life This innovative design of the GSX actuators produces smooth, accurate and programmable linear motion that is precisely synchronized with the armature rotation.

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Stay logged in on this computer. Forgotten password. Loosen the two Phillips screws on the correct cable strain relief to allow enough space for the cable to exit without binding when the box is extended. After installing the cables, retighten the two screws.

This package, plus the high functionality of DIGITAL's microcomputer products, allows LSI microcomputer applications to be implement- ed within a space smaller than that required for many eight-bit sys- tems. User suppl ies cord for other power requirements. Two types of mounting hardware let the BA VA be used as a tabletop unit or be attached to a flat surface in any plane. The BA VA does not generate a signal for use as a line-time clock in the processor module.

If this function is required, the MXV11 multi- function module, which includes a 60Hz clock, should be used. If powerfail capability is needed, external hardware is required. For applications where the mounting of the BAVA prevents easy user access to the chassis, the capability is provided for adding an external restart switch. Momentary closure of this switch causes the proces- sor to go to the user-selected powerup mode for the system.

The powersupply has more capacity than normally used by the four LSI bus modules that can be mounted in the chassis. Therefore, a.

The SA VA powersupply can be configured through selector switches to operate throughout the world. FOR ". These programs are user-selectable by setting dip switches. The diagnostic programs test the processor, the memory, and the user's console. The bootstrap programs are used to boot a number of LSIcompatible peripherals. The module also contains ohm bus terminator cir- cuits. The module also has four programmable light-emitting diodes LEDs that indicate a failure in a program and monitor the tests in progress.

All the switches and indicators are edge-mounted on the module for easy access. The revision 0 module was produced in limited quantities and does not incorporate all the characteristics of revision A. The differences between these modules are listed at the end of this section. The transceiver and control functions control the transfer of data between the bus and the BDV The ROM address function is also used to transfer data into the data selection function.

Then data is placed on the LSI bus by the control and transceiver functions. If a register was addressed, the transceiver logic generates the address match signal that activates the control logic. The control logic is enabled by the address match signal from the transceiver logic. The bus control signals are defined in the appropriate processor hand- book. When the registers are to be written into, the XMIT signal is negated and the registers are placed into a load condition. The regis- ters are clocked and the information on the DAL lines is loaded into the registers as data.

The registers are cleared when power is turned on or when the system is booted. Each ROM has 10 addresses available. The logic selects the high byte of the peR register if bit 8 of the LSI bus is one and selects the low byte if bit 8 is a zero. The selected byte is shifted to the right one bit and used as the high byte of the BDV11 address.

Socket Selection The socket or ROM selection logic Figure 2 consists of two decod- ers E30 and E35 that provide the outputs used to select the high byte and low byte sockets. The user can program A10 Hand A14 H inputs to these decoders by selecting jumper wires W1-W4 and W9-W12 to determine the configuration designation described in Table 2. A The output data from the ROMs is sent to the data selector logic.

This data is stored until the outputs are enabled by XMIT. Display The display logic consists of four flip-flops and four LEOs. The contents of the display register address are gated into the flip-flops and the outputs light the display LEO indicators. The pattern of the display indicates to the user the type of program error when a failure occurs. The processor enters the halt mode and responds to the console OOT commands. When the capacitor discharges, the BOCOK H signal is enabled, the processor carries out a power-up sequence, and normal operation is resumed.

The user can modify the configuration for his own software requirements. Thirteen jumper wires are located on the module as shown in Figure 3 and identified in Table 1. Eight are used for selecting sockets, and five are used to ac- commodate various types of memory chips. The switches used to se- lect programs are listed in the Programming section below.

Socket Selection The socket selection logic is controlled by jumpers W1-W4 and W9- W12, which can be configured in seven different ways, as shown in Table 2. Group A assigns the PCR pages and socket selections. B NO :I;W Memory Configuration The user can change the configuration of the BDV11 memory struc- ture by using socket selection jumpers W1-W4 and W9-W12; the stan- dard configuration is in Table 2.

Details about selecting a configuration using the socket se- lection jumpers are shown below. These registers are assigned individual addresses that cannot be changed or modified. The registers are described in the following paragraphs; their designations and addresses are listed in Table 4. The PCR is a bit register that consists of two 8-bit bytes. The low byte consists of bits and the high byte consists of bits When the low byte of the PCR is equal to page 6, then bus addresses accesses the ROM locations in the block When a bus address falls in this range, the logic considers only the low byte of the PCR.

However, if the bus address is in the range , only the high byte of the PCR is used to select the ROM location. CB2 and DB2 must be supplied with external -5 V power.

The PCR bytes can be loaded separately. To select ROM locations , for instance, one need only load the PCR high byte with page 7; thus, the high byte contains , while the low byte can contain anything. Configuration Register - This bit read-only register is used to select for execution diagnostics or bootstrap programs for mainte- nance and system configuration.

Bits of the register are set by switches E through E and E through E When bits of the register are set, then the corresponding LEDs are off. Four LEOs indicate when a program fails. The switches and LEOs are shown in Figure 4. Switches A1-A8 represent switches The pro- grams selected by these switches are listed below. These 12 switches make up the configuration register that can be read at address A2 ON Execute memory test upon power-up or restart.

The first word of each word segment is read and then written back into itself. Allowed responses are a 2-character mnemonic with a 1-digit octal unit number or one of two special Single-character mnemonics. The special single-charac- ter mnemonics are: y Use switch settings to determine boot device N Halt-enter microcode DDT.

All unused patterns or mnemonics will default to ROM boot if switch 82, 83, or 84 is on. If present, the ROM boot is invoked. The mnemonic's first character is placed in the high byte location of 2. Location 0 is loaded with the binary unit number.

If an unrecognized switch setting is encoun- tered instead, a copy of the switches is placed in location 2 with bit 15 set. If no additional ROM exists, the switch-checking routine will halt or the mnemonic routine will reprompt. The above features let the user implement additional features or boots in additional ROMs without changing to the base ROMs.

Diagnostic Lights When a failure occurs in a diagnostic test or in a bootstrap program, the diagnostic light display indicates the area of the failure as shown in Table 8. A failure causes the error to be indicated by the display and an error halt instruction is carried out by the processor.

When entering the halt mode, the processor outputs the PC address at the time of the error on the console terminal. The actual error address is one word less than the terminal printout.

In the halt mode, the processor re- sponds to console OOT commands and the operator can troubleshoot the error. Table 9 lists the possible address and the cause of some errors. When the switch is on closed , the LTC function is program-controlled, i. While in the halt mode, the processor can execute single in- structions for system maintenance.

Program control is reestablished by returning the switch to the ENABLE position and entering a "P" command at the console terminal providing the contents of register R7 were not changed. Refer to the appropriate processor handbook for a description of console OOT command usage.

On On On On System hung; halt switch on or power-up mode wrong. Off On Off Off Waiting for response from operator. Off On Off On Load device fault. Write address into itself. Error in switches. CSR address for selected device. RO contains address of error. Data test failed. Write and read bytes failed. Checksum on data block. Checksum on address block. Jump address is odd. RO pOints to cause of error. Match was not made with switch- es.

No done flag. Thus, for maintenance purposes, the system can be rebooted at any time. This block resides in the upper 4K address bank 28KK , which is normally used for peripheral-device addressing, and consists of byte addresses The peR is loaded with "page" information, i.

For example, if the peR contents represent pages 0 and 1, then bus addresses access ROM locations ; if the peR contents repre- sent pages 10 and 11, then bus addresses access ROM locations Table 10 relates bus addresses, peR pages, and ROM locations.

Furthermore, the sockets are assigned specific kinds of ROMs, as Table 11 indicates, e. There are eight locations on the BDV11 printed circuit board in which jumpers are inserted selectively to achieve these assignments.

The format is a modified version of absolute loader paper tape format. The standard format consists of sequential blocks, organized by byte, as follows: 1 BYTE This indicates start of block.

BCl low-order eight bits of byte count. BCH High-order eight bits of byte count. ADl low-order eight bits of load address. ADH High-order eight bits of load address. DATA Sequential bytes of data. CKB Checksum byte. These frames are repeated as required until a starting address block is encountered. This is indicated by a byte count of six, which is too short to allow a data field. The load address of this block is used as the starting address. The format skips every th and th location in the ROM pattern.

This block will overlay previously loaded data. It is pro- grammed by the CPU to operate either in 8-bit or bit mode with asynchronous baud rates varying from to Simulta- neously, it can receive serial data streams and convert them into par- allel data characters for the CPU. The DLART also has an internal baud rate control to reduce support logic and provides four realtime interrupt outputs to support dynamic memory refresh for realtime system applications.

The chip is fabricated in N-channel MOS silicon technology. Asserted Pin No. When this line goes from as- serted to unasserted while WLB is asserted and AO is unasserted, data on the low byte of the DAL lines is written into the writable bits of the register selected by the A2, A1lines. Name State Description the register selected by the A2, A1 lines. This line has no effect on internal registers if CS is unas- serted or AO is asserted. The drivers will go inactive tristate within 50 ns whenever one or more of the following occurs: 1 CS goes unasserted, 2 RD goes unasserted, or 3 WLB goes asserted.

Reading is normal, but at- tempts to write have no effect. After being high for a minimum of ns, this output can be cleared externally by being forced low clamped to ground with an open collector transis- tor for a minimum of ns. This output can also be cleared externally by being forced low clamped to ground by an open collector transistor. Name State Description for a minimum of ns after being high for a min- imum of ns.

The input signal must remain in the high marking state for at least one half bit time be- fore a high-to-Iow mark- to-space transition is recognized. A mark-to- space transition is re- quired to determine the beginning of a start bit and initiate data recep- tion.

This output. Name State Description can also be cleared exter- nally by being forced low clamped to ground by an open collector transistor for a minimum of ns after being high for a min- imum of ns. This line re- mains high marking when no data is being transmitted. All baud rates and clocks are derived from this input. This output can also be cleared externally by being forced low clamped to ground by an open collector transistor for a minimum of ns after being high for a min- imum of ns.

After being high for a minimum of ns, this output can be cleared externally by being forced low clamped to ground with an open collector transistor for a minimum of ns. Name State Description. These inputs are op- tionally asserted low externally by a jumper to ground or held high inter- nally.

The receiver and transmitter baud rate is determined by these lines when the PBRE bit is clear. It is also used in a system during powerup to reset all internal logic. An overrun error indicates that reading of the previously received byte was not completed prior to re- ceiving a new byte. These bits are cleared by TEST. Reading the contents of this register causes no other effect.

This register is cleared by TEST. These bits are. When this bit is set, the transmitter serial output is connected to the receiver serial input while disconnecting the external seri- al input. When set, the baud rate is determined by the PBR2- obit in this register. When clear, the baud rate is deter- mined by the BRS pins.

Symbol Parameter Min. This is a stress rating only and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may af- fect device reliability.

This signal should be used to gate the appropriate vector ad- dress onto the bus and to form the bus sig- nal called BRPLY L. This sig- nal is the daisy-chained signal that is passed by all devices not requesting inter- rupt service see BIAKI L.

This signal is daisy-chained such that the first requesting device blocks the signal propagation while non-requesting devices pass the signal on as BIAKO L to the next device in the chain. This signal is gener- ated when this device needs to interrupt the processor. The request is generated by a false to true transition of the ROST signal along with the associated true interrupt en- able signal. This signal line normally remains asserted until the re- quest is serviced.

TTL Input High-level input current 50 p. A max. Low-level output voltage 0. Bus Hi Z input and open collector outputs. Bus Inputs High-level input current 40,uA max. BV Low-level input current ,uA max. Bus Outputs Low-level output voltage O. BV max. At the assert edge of this signal, address information is trapped in four latches.

This is a strobing signal to ef- fect a data input transaction. This is a strobing signal to effect a data output transaction. Used to gate read data from a selected register onto the data bus. Out High Byte. They indicate that a word register has been selected for a data transaction. The external resistor should be tied to Vee and the capacitor to ground.

This set of four lines constitutes 11 BUS1L the bus side of the transceiver. Open collec- 9 BUS2L tor outputs; high-impedance inputs. When in transmit data mode, the data carried on these lines are passed inverted to BUS When in the disabled mode, these lines go open HI-Z. A high will cause a one low to be transmitted on the bus pin. A low on this line will enable the Match output.

A strap to ground on 1 JA1 L these inputs will allow a match to occur with 2 JA2 L a 1 low on the corresponding BUS line; an 19 JA3 L open will allow a match with a 0 high ; a strap to Vee will disconnect the corres- ponding address bit from the comparison. LA max. Address and interrupt vector information for interrupt request and device selection is also provided by the DC The device address is set up using input lines A3 through A12, while the interrupt vector address is set up using input lines V3 through VB.

The protocol logic DC "functions as a register selector to provide. The end of this delay will initiate a reply to the CPU indicating that the address has been received. The interrupt logic DC performs an interrupt transaction. Two channels A and B are provided for generating two interrupt requests, with channel A having the highest priority.

The interrupt enable flip- flop within the interrupt logic must first be set when the user's device is to interrupt the LSI The interrupt logic available to the user indicates the status of the interrupt logic enable flip-flops.

Each line is asserted logic H when the appropriate interrupt enable flip-flop is set. These status lines can function as part of the user's control status register CSR. II"'Y L ao.. The device is used in peripheral interfaces to provide two interrupt channels la- beled "A" and "8," with the A section at a higher priority than the 8 section.

Bus signals can directly attach to the device because receivers and drivers are provided on the Chip. How- ever, the DC is now ordinarily used with the user's three-state bus to limit Bus loading. An RC delay circuit is provided to slow the re- sponse of the peripheral interface to data transfer requests. External RCs can be added to vary the delay.

It also includes a comparison circuit for device address selection and a constant generator for interrupt vector address generation. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs and 20 mA, tri-state drivers. Data on this port are the logical inversion of the data on the bus side. Three address "jumper" inputs are used to compare against three bus inputs to generate the signal MATCH. The address jump- ers can also be put into a third logical state that disables jumpers for "don't care" address bits.

Three vector jumper inputs are used to generate a constant that can be passed to the computer bus. The three inputs directly drive three of the bus lines, overriding the action of the control lines. Two control signals are decoded to give three optional states: receive data, transmit data, and disable. This example is the interrupt enable bit for interrupt A which connects to bit 6 of the example CSA.

This signal controls the least significant bit of the A counter. When high, the LSB is prevented from toggling, hence the counter increments by two. When two counters are cascaded, CNT1A on the high- order counter should be grounded. This clock signal increments the A counter on its negative edge. The counter is incre- mented by one or two, de- pending on CNT1 A.

This clock signal increments the C counter by one on its ne- gative edge. This signal allows the selection of the A counter according to the truth tables. This signal allows the read operation to take place according to the truth tables. When this signal goes through a high-to- low transition, the load opera- tion is allowed to take place according to the truth tables. No data changes permitted while LD is low. These eight bidirectional lines are used to carry data in and out of the selected counter.

TTL Outputs High level output volt- 2. A high on this signal initiates the bus re- quest transaction. A low allows the termination of bus master- ship to take place. A high on this signal allows a maximum of four transf-ers to take place before giving up bus mastership.

A low dis- ables this feature and an un- limited transfer will take place as long as REO is high. If left open, this pin will assume a high state. This signal allows the selection of the type of transfers to take place ac- cording to the truth table. This signal allows the selection of the type of transfer to take place according to the truth ta- ble.

During a DATIO transfer, this signal must be toggled in order to allow the com pletion of the output portion of the transfer. If left open, this pin will as- sume a high state. This signal allows the de- vice to become master according to the following re- lationship:. This clock sig nal used to generate all transfer timing sequences. This signal is used to enable or disable the clock signal.

RPL Y H. This sig- nal is used to initialize the chip to the state where REO is needed to start a bus reqest transaction. A low on this signal indicates that the device is re- questing bus mastership. This output may be tied directly to the bus. A high on this signal indicates that the device has bus mastership and a transfer sequence is in progress. This signal is the delayed version of BDMGI if no request is pending; other- wise, it is not asserted.

This signal is assert- ed by the device to indicate that a transfer is in progress. This signal is asserted to indi- cate that data may be placed on the bus. This signal is asserted to indi- cate that an address may be placed on the bus. This sig- nal is asserted to indicate that the bus master device is ready to accept data.

This signal is asserted to indicate that the bus master device has output valid data. Low level input current Viol LtJl. Device address and vector switch inputs to the transceivers provide convenient address and vector selection. Switches A3 through A 12 are the device address selection switches and switches V3 through V8 are for vector selection. Switches are ON. The remaining register addresses are then properly decoded as sequential addresses beyond the bus address register Figures 2 and 3.

The DC is the internal register selector. This integrated circuit monitors BDAl lines 0, 1, and 2 to determine which register address has been placed on the lSI bus. When an address for an internal register is placed on the lSI bus, one of the SEl outputs from the DC is driven low. Internal register selection is summarized as follows: Control Line Select Register. The DC integrated circuit was designed to operate directly from the lSI bus. Because of this inversion, it is necessary to change the nomenclature.

The DC IC performs an interrupt transaction that uses the daisy- chain type arbitration scheme to assign priorities to peripheral de- vices. The DC has two channels A and B for generating two interrupt requests. Channel A has higher priority than channel B. If a user's device wants control of the LSI bus, the interrupt enable flip- flop within the DC must be set. RQST must be held asserted until the interrupt is serviced.

Interrupts are produced for bus time-outs CSR bits 15 and 14 and at the completion of a block trans- fer CSR bits 7 and 6. An 8-MHz free-running clock is provided by E This clock is used by the DC to generate all transfer timing sequences.

The actual clock frequency is not critical and can be any frequency up to 8. An RC time constant providecrby resistor R14 and capa- citor C2 provides a delay for the reassertion-. This allows other direct memory access devices to obtain the bus during the time the CNT4 logic releases the bus and re-requests the bus. R12 Rl0 Figure 4 Typical Applic? User devices initiate bus requests by driving the set input of the re- quest flip-flop E10 low.

WCNTO then resets the request flip-flop. The least significant bits of the word count and bus address register and register C is the word count register. Both registers can be read or written under program control from the LSI bus. The bus address register is incremented by two for word transfers. Initially, the word count register is loaded under program control, with the 2's complement of the number of words to be transferred.

As words are transferred, the word count register is incre- mented toward zero. The data passes through the drivers, is applied to the internal 3-state bus and, via the DC transceivers, to the LSI bus.

Miscellaneous Logic Miscellaneous logic is shown in Figure 5. These signals are gated to produce enable signals for the CSR, the output buffers, and the input drivers. This prevents hanging-up the LSI bus for peri- ods longer than 10 Ils. This flip-flop is automatically reset during power-up. Normally, the transceivers are in the receive state to accept device addresses from the LSI bus. Figure 6 shows the GSR format. In this partic- ular application, the s are permanently enabled by grounding pins 7 and 9.

When set to 0, the in- terrupt is inhibited. This bit is always read as a zero. This is an ex- ample for test purposes. When set to a 0, the inter- rupt is inhibited. Bit 14 must be set 1 to enable the bus time-out interrupt. Its primary use is in DMA peripheral device interfaces. Two DC ICs may be cascaded to increase register implementation. Both counters may be cleared simultaneously. Each counter is separately loaded by LD and the corresponding select line from the protocol chip.

Each counter is incremented separately. The we counter word byte counter is always incremented by one; the A counter bus address may be incremented by one or two for byte or word addressing, re- spectively. Data from the De Ie is placed on the 3-state bus via internal 3- state drivers.

Each counter is separately read by RD and the corres- ponding select line. This device provides the logic to perform the handshaking operations required to request and to gain control of the system bus.

The DC IC has a control line that will allow multiple transfers or only four transfers to take place before giving up bus mastership. Figure 9 is a simplified logic diagram of the DC IC. The logic sym- bols and truth table are presented in Figure The DDV is a 9 x 6, slot backplane with a 9 x 4 slot section 18 individual double-height or nine quad-height module slots prebused specifically for LSI bus signal, power, and ground connections.

The etched board completely overlays the entire pin side of all connector blocks and is recessed sufficiently to allow wirewrapping on those same pins with AWG wire. An optional cardcage, type H , is also available to provide protec- tion against physical damage to modules and to serve as a cardguide. The cardcage completely surrounds the slot side of the system unit and is shown in Figure 1.

The position numbers indicate the bus-grant wiring scheme with respect to the processor module. The bus-grant signals propagate through the slot locations in the position order shown in Figure 2 until they reach the requesting device.

Any unused slots must be jumpered to provide busgrant signal continuity, or it is rec- ommended that unused locations occur only in the highest position- numbered locations. Rows E and F contain the 18 user-defined slots with power and ground connections provided. The overall dimensions of the unit are shown in Figure 3. The H mounting frame of the DDV is provided with tapped holes and clearance holes to enable the attachment of the system unit. H Card Assembly Mounting The card assembly provides nylon guides which help to guide and support the modules installed in the system unit.

The H card assembly is supplied with the hardware necessary to mount to the H mounting frame. Figure 4 shows the method of assembly. Two screws item 2 and two washers item 1 are inserted through the clearance holes of the PC board and H mounting frame and into the two threaded inserts on each bracket of the card assembly. DCOK Hi The power and ground leads from the external source connect to the seven-position terminal board mounted on the edge of the PC board as shown in Figure 3.

Any suitable connector terminals, solder, or crimp style, can be attached to the powersupply leads and inserted under the terminal strip screws. The de- scriptions of the registers and their standard factory addresses are listed in Table 1. Available jumpers are shown in Figure 1 and their applications are listed in Table 2. Second Register Mnemonic Console Module. The least-significant-three bits only bits 1 and 2 are used; bit 0 is ig- nored address the desired register in the DLV11, as described in Ta- ble 1.

Address bits 3 through 12 are jumper-selected, as shown in Figure 2. Since each DLV11 module has four registers, each requires four ad- dresses. Addresses are reserved for the DLV11 used with the console peripheral device. Por isso, a Compumicro tem uma faixa especffica de clien- tes. Assim Ernesto Marques Camelo, um dos s6cies da Compumicro, de- fine a empresa. Os produtos oferecidos pela Compumicro sdo: Unitron "o Apple cujo fabricante nos inspi- ra maior confianpa".

Nexus "da linha de 16 bits, a Scopus foi escolhida per ser unria em- presa apta a acompanhar a eve- lupde dos produtos IBM" e im- pressoras Elebra, Elgin e Scrit- ta. Nenhum micro TRS, pels "d uma linha que jd morreu". Errtesto Camelo explica que OS PC-likes tdm nas organiza- pSes de grande ports Ibancos e financeiras e na drea de siste- mas centres de processamento de dados os seus grandes com- pradores: "os primeiros comple- mentam suas necessidados com o PC nacional para evitar pro- blemas com a fiscalizapde, e os segundos aceitam agora a naces- sidade de substituipdo de termi- nals por micros, principalmente quando sdo de tecnologia IBM".

As vendas sSo dirigidas, co- me se pocte observer, a um pu- blico especffico: "No andar de um edifCcio d rare entrar in- ceutos. As pessoas que nos pre- curam vdm geralmente atravds da propaganda cliente a cliente. Tamos tambdm uma equipe de vendas externa, a publicidade em veTcutos adequades e um bam numere de clientes e con- tatos do tempo em que traba- Ihamos na Computique e na Clappy".

Mas seja o cliente uma pe- quena, mddia, grande empresa ou um profissional liberal, Er- nesto garante que ele jd chega d Compumicro sabendo qual o problema que pode ser resolvi- do com a ajuda do micro. A equ ipe entdo anal isa e deter- mine o tipo de sistema adequa- do ao cliente e faz a demonstra- pdb.

Os programas tambdm sdo demonstrados ao cliente. Se ele quiser, a Compumicro desenvol- ve um software especi'fico para ele, mas "preferimos selecionar um pacete que jd exista no mer- cade. Quanto d assistencia tdcnica, Ernesto segue um pensamento que sempre defendeu: ela deve ser prestada pelo fabricante e ndo pelo revendedor.

Ouante ds formas de venda, aldm das tradicionais, a Compu- micro eferece uma nova modal! As prestapOes sdo fixes e que 6 uma vantagem am re- lapse ae leasing e variam de 12 a 18 meses".

A Compumicro Informdtica Empresarial Ltda. Infermapoes pelo tel. Escolhendo uma, o computador plotard no video a figura requisitada, solicitando ao usudrio entrar com as medidas necessirias aos cdlculos. Ao infomid-las, deve-se ter o cuidado de usar sempre a mesma unidade de medida, pois o programs nSo faz conversCes.

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Dividido em duas partes, "As instnji? Temos toda linha de perifericos e suprimentos para acom- panhar o crescimento de sua empresa. Tambem ndo era para menos. E quem estd no mer- cado de informdtica sabe que somente o Nexus pode ofe- recer esta garantia.

Fomeci- mento hoje e amanhd. A garantia e assisten- cia tecnica oo Nexus e prestada diretamente pelo fabricante, em todo pais. Com o Nexus seu micro ndo fica parade. A Compumicro e o fabricante garantem. Levantamento de necessidades, especificapao de configuragoes, treinamento, for- necimento de Software nacional e importado, desenvoivimento e implantagao de sistemas, com a garantia da experiencia de quem mais entende de 16 bits no Brasil. Rua Sets d« Setambro. Pena, , cj. Tratar com tel.

Rua Josafa Belo, Tel. Turmas reduzidas, certificado de conciusao e aulas prSticas. Infor- macoes na Av. Passos, - sala 21 5 ou pelo telefone 1 Hordrio diurno e noturno, insc. Turmas redu- zidas, certificado de conciusao e aulas prSticas. Pedidos pe- lo telefone: ramal ou com Daniel. Com Jamel - Ox, Postal - Apenas 15 mil. Escrevam pedindo catdlogo para: Eletro Soft, Cx. Postal - Sao Carlos, S. Cata- rina, CEP: Fone: Oil -CEP X 0,00 por fita — cheque nomi- nal ou reembolso postal.

Desk Eng. Postal - Tratar com Andrfi no perfodo da noite, pelo fone ou enviar carta para Rua Dr. Remeierei selos e en- velopes »ra a remessa de progra- mas. Basta pagar uma taxa de 8 mil e contribuir com um livro, terS di- reito a usar um micro por lOhs ao mes e acesso a biblioteca.

Rua Visconde de PirajS, lj. Isso tanibAm 6 decitio sua. Be 6 com palivel com todos os prog ramas do f amcao Sirwiair e poasui equlpamenlos periencos eotduslvoaqijesTipHarrTiuitoaSLiacapacklade. Tenho que desligar e ligar novamente para recomegar a dlgi- tagao. Se for as- sim, 4 algo facil de ser resolvido? Se isso 4 verdade, quais sao? Se nao 6, como devo proceder? Sergio Meira. I eodo CP Mod. Eu ji tentei com um editor Assembler para o TRS, mas ao termlnar de carregar o progra- ma, apareceram caracteres estranhos no v deo.

Se o monitor residente do CP for suficiente, como devo proceder? Ill, e podem ser perfeitamente utilizados no CP ou CP E 6 relativamente fdcil conseguir uma c6- pia com um colega ou mesmo atraves da Se?

Marcelo B. Silveira, SP. O passo seguinte i resolver o sistema triangular definido pelos n Ij i. Vejamos um exemplo. A Nasajon Sistemas tambem dcsenvolve qualquer tipo de software especi'fico. Venha ver como i importante fazer um programa diferente paia o seu computador. Progiama Av. Rio Branco, 45 grupo 1 Tel.

Paraganhar tempo de com- putagao, no lugar de efetuar a troca, esta e guardada num vetor da memoria. Para rea! Prentice-HaJI O TI e mais novo microcomputador da Unitron. Ele tern um mi- croprocessador e um teclado inteligente. Isto e, um teclado gerador de caracteres para a lingua portuguesa.

Vela que este teclado pode fazer : Um. Redefinigao das posigoes da tecla pelo proprio usuario. Repetigao automatica de carac- teres. Alias, na Clappy voce encontra tudo o que precisa em microcomputadores, perifericos, suprimen- tos, softwares. Alem de cursos proprios de programagao e operagao, assistencia tecnica, implantagao e instalagao de siste- mas.

E mais. Aplicativos comerciais: contabili- dade, controle de estoque, f olha de pagamentos, contas a pagar e a receber. Aplicativos de apoio: planilha f inanceira , processa- mento de dados, mala direta, caoastro e controle financeiro, graficos, etc. Seja por venda, seja por leasing, ninguem pode fazer um preco melhor do que a Clappy.

Rio Branco, 12 - loja e sobreloja. Sete de Setembro, loja Q galeria Tel. Estacionamento proprio. Listel responde Aideia que motivou a elabora- deste programa foi a de conseguir processar infonna- em cadeias de caracteres no micro HP Como se sabe. Poris- so. Assim, atraves das teclas de- finidas pelo usuirio vide figura 1 , ele pode acessar o arquivo central pelo no- me, endereco ou telefone.

Pressionando-se a tecla especial LISTAR, por exemplo, todos os nomes inclui'dos no arquivo serao listados em ordem alfabetica, seja qual for a ordem em que os dados tenham sido introduzi- dos. Perguntas que devem ser respondidas com sim ou ndo preci- sam apenas de um S ou N. Lembramos ainda que o niimero maximo de entra- das e , o que pode ser modificado conforme a capacidade de seu equipa- mento.

Este programa roda em um HP- 85 em sua configura9ao basica, ocupan- do bytes. Atualmente 4 consultor financeiro autdnomo. Elimine as linhas 5 a 95, pois essa parte do programa nao seii mais utilizada. O restante linhas a 1 SO , usaremos novamente para a gravagSo do que for digitado este mes este, alias, seri o procedimento para os pr6ximos meses. Deveri aparecer o nome no topo do video e, na parte inferior, o cursor.

Vejamos como se processa, dentro de SKEY, o reconhecimento de uma tecla. Devemos partir do princi'pio de que, a toda hora. Sua funfao t organizar a entrada de paiimetros via teclado. Feito isso, SORG retoma ao ponto em que foi chamada. Se o carrier for omitido. F Ident i f i ca o caracter. A prdxima rotina do sistema operacional a ser utilizada 6 a que inicia no enderefo 09D8. Isso 6 feito pela rotina E, lembrando que, i quantidade solicitada pelo usudrio, deverao ser acrescidos mais 6 bytes: numero da linha 2 , quantidade de elementos 2 , c6digo da instrufSo REM 1 e o ENTER do final 1.

Sao Jooo. Embora tenhamos remetido todas as colaborapoes que nos chegaram para o Decio por uma questao de espapo selecionamos apenas uma para publicagao. Paulo Alfredo Lucena Borges-RS Oponto de partida do gerador de numeros aleatdrios e a formula que vai gerar estes numeros e possi'vel que algum purista diga que.

Apos esta escolha. Quanto aos demais dados. Rua Aurora. Ses Patrimoniais. Observa9ffo: case a empresa nSo possua tres balances, deve-se atribuir para os dados relatives aos anos em que nSo te- nha balance o valor 1.

Esta compara? Quando o quociente for menor que a unidade. Atraves deste quociente, pode- mos avaliar a poii'tica de investimento que a empresa adota. Este quociente revela a capacida- de da empresa em saldar as suas obriga- 9 5es a curto e a Iongo prazo, fazendo uso dos recursos financeiros disponi'veis e venci'veis para o mesmo pen'odo.

Atraves deste quociente conhecemos a situagao de solvabilidade da empresa face ks suas obriga95es, depois de recebidos os eru- dites. Convem salientar que, para o cilcule deste quociente, no realizavel a curto prazo nSo e consideiade estoque. Este quociente representa a capacidade de so- lu9ao de compromissos venci'veis dentro de curto prazo. Cada vez que a receita operacienal atinge valer do capital prbprio, significa que ele fei mevimen- tade uma vez.

A rota9Se de capital pr6prio e' de grande importancia, uma vez que do nu- mero de rota9aes depende e resultade economico final. Este quociente revela a eficiencia da empresa em obler de suas atividades, sua margem de ganlio sobre a receita. Isto nos dd uma margem maior de escelha, ou seja, podemos utilizar parametros com pouca ou nenhuma importancia conceitual.

Partinde desta premissa, analisaremos a situa9So economico-financeira das em- presas atraves dos dez quocientes ]i identificados, mais os que normalmente sSo aplicados em uma andlise. Os dez quocientes nos dSo subsidies suficientemente abrangentes para poder- mos avaliar o equili'brio economice-fi- nanceiro das empresas. De posse da situa9ao estitica patri- monial, situa9ao dinamica patrimonial e dos quocientes calculados com base nos tres liltimos balan90s, analista poderd.

Alem de outros pro- cedimentos. A exclusSo de- ve-se ao fato de que procurou-se elabo- rar um modelo de anilise que pudesse ter aplica9ao em quaJquer setor da eco- nomia no qual as empresas estao integra- das. Acrescentando es- te parametro,estariamos prejudicando a universal idade do modelo, uma de suas principals caracteristicas.

Curitiba, PR. Sequencia de entrada de dados no programa a RazfTo social da empresa; b Tipode atividade; c Anos a serem analisados; d Introdu9So dos valores das seguintes contas para cada ano: l Disponivel 2 Realizavel curto prazo 3 Realizivel longo prazo 4 ImobilizafOes — depreciagOes 5 Estoque 6 Capital social 7 Naoexig]vel 8 Exigi'vel curto prazo 9 Exigi'vel longo prazo 10 Ren da operacional 11 Lucre bruto 1 2 Lucro operacional 13 Lucro liquido; e Op?

Clovis Bevilacqua, ? ECC U. BHE U. BTTE U. I Economizar 4 a ordem do dia. Mas se transfor- mamos as tres variaveis em uma s6,gra- vamos apenas uma, o que resulta numa grande economia de tempo, piincipal- 66 Roge Rosofini mente se temos cinco ou seis variaveis. Para juntarmos as tres variaveis em uma so. Para gravar nossas tres variiveis nu- mericas anteriores.

Entretanto, deve-se tomai cuidado para que o comprimento de ZS no caso nao ultrapasse ca- racteres. Acompanhe este processo na figura 1.

Se programa tiver sido gravado em ve- locidade baixa. Junto com Fernan- do Coura. O cominho esta aberto para voce na 11? FUSE, de 20 a 24 de junho. Alios, essa e a epoca mals propicia para investir e acompanhaf as atuais conquistos desse mercado. Hua Brasilio Machado. Veiculooiicial: KM. Arquivo de comunicados Este programa foi desenvolvido com objetivo de facilitar a ta refa do radioamador no preen- chimento de cart5es QSL e do Registro de Comunicados LOG , e esti pronto para ser utilizado em micros da linha TRS, versao disco com impres- sora.

Vamos entao aos detalhes do progra- ma. A seguir, o micro passa a solicitar, na terminologia mundialmen- te adotada. O programa nao foi desenvolvido es- pecificamente para registrar comunica- dos ao mesmo tempo em que est - sen- do realizados, por uma linich "-azao: sem- TD RADIO! C 2-URY R. C 2-UnY R. Sugiro que o nome seja iniciado com as letras QSO, seguidas do mimero de ordem do arquivo, da letra Q e de um ou dois algarismos que representem a quantidade de comunicados arquivados.

Seria interessante utiJizai um linico disco para o programa e todos OS arquivos. A formata9So da im- pressSo 4 para etiquetas em uma coluna de 2. Nota de PYID WM: se voce conseguir formuldrio continuo de maior gramatu- ra, tipo cartolina, poderd modificar esta opgao para imprimir, em vez de etique- tas.

Mon- de noticias. A formata d para formulario de 80 cotunas. Embora o tempo deconido entre o lancamento do numeio 31 e fechamento deste tenha side bastante pequeno, podemos, quer pela conespondencia recebida, quer pwlos comentarios nas faixas, antecipar seu sucesso.

De infcio quero pedir descuplas ao amigo e colaborador Pivatto-PY3IT pela publi- cacao incoiteta de seu indicativo - macanudo que se preza munheca logo na entrada. Antes de continual, um parentcsis: alguns colegas reportaiam diiiculdades na digita- fio do Professor Picapau MS n9 31 , pois a impressora usa o mesmo carater para o al- gaiismo zero e a letra O, o que causa alguma confusao nas linhas Da mesma Forma, serSo feitas referencias a Boletins Informativos, QTCs falados e demais publica- ns semelhantes que nos sejam enviadas.

Os' radio-escutas ou os que nSo tern QSL podem mandar uma cartinha. Agora ja vou indo, mas antes desejo ressaltar o transcurso no dia 5 de maio do Dia das Comunicagoes.