Vector processing in computer architecture pdf

A block diagram of a modern multiple pipeline vector computer is shown below: A typical pipe lined vector processor. Recommended Articles. Article Contributed By :. Easy Normal Medium Hard Expert. Writing code in comment? Please use ide. Load Comments. What's New. Most visited in Misc. Generally, a bus consists of multiple communication lines or pathways. Each pathway is capable of transmitting signals representing the binary 1 and the binary 0.

An 8-bit unit of data will be transmitted over eight bus lines. A4: Minimal sum of products mSoP : A sum of products expression is minimal if all other mathematically equivalent SoPs 1. Minimal product of sums mPoS : A product of sums expression is minimal if all other mathematically equivalent PoSs 1. Average rating 4. Vote count: No votes so far! Be the first to rate this post. Your email address will not be published. How useful was this post?

Click on a star to rate it! Baba Deva February 18, at pm. Smartzworld February 19, at pm. Leave a Reply Cancel reply Your email address will not be published. Leave this field empty. Below we have classified the vector instructions in four types. Here, V is representing the vector operands and S represents the scalar operands. In the figure below, O1 and O2 are the unary operations and O3 and O4 are the binary operations.

Most of the vector instructions are pipelined as vector instruction performs the same operation on the different data sets repeatedly. Now, the pipelining has start-up delay, so longer vectors would perform better here. The pipelined vector processors can be classified into two types based on from where the operand is being fetched for vector processing. The two architectural classifications are Memory-to-Memory and Register-to-Register.

In Memory-to-Memory vector processor the operands for instruction, the intermediate result and the final result all these are retrieved from the main memory.

In Register-to-Register vector processor the source operands for instruction, the intermediate result, and the final result all are retrieved from vector or scalar registers. Cray-1 and Fujitsu VP use register-to-register format for vector instructions. Operation code indicates the operation that has to be performed in the given instruction. It decides the functional unit for the specified operation or reconfigures the multifunction unit. Base address field refers to the memory location from where the operands are to be fetched or to where the result has to be stored.

The base address is found in the memory reference instructions. In the vector instruction, the operand and the result both are stored in the vector registers. Here, the base address refers to the designated vector register. A vector operand has several data elements and address increment specifies the address of the next element in the operand.

Some computer stores the data element consecutively in main memory for which the increment is always 1. But, some computers that do not store the data elements consecutively requires the variable address increment. Address Offset is always specified related to the base address.

The effective memory address is calculated using the address offset. Vector length specifies the number of elements in a vector operand. It identifies the termination of a vector instruction. In vector processing, we come across two overheads setup time and flushing time.